As the DRAM cell is scaled towards the 256 Mb DRAM and beyond, innovative cell concepts are needed to push the cell area to practical limits. One such concept is to reduce the cell area by forming two trenches using the trench opening for one. This technique can be used to reduce the cell area of folded bitline cells to six or four lithographic squares (using two levels of wiring to form bitlines), and to reduce the cell area of open bitline cells to two lithographic squares. Although cell structures using such concepts as a buried trench cell have been proposed in the past, these structures rely on expensive selective epi growth techniques to reduce the trench opening. Selective epi growth, however, typically has a very high defect density and therefore is generally considered to be unsuitable for DRAM applications.
Thus, a need has arisen for a DRAM cell structure that can take advantage of the area minimization benefits of prior art trench-under-access device techniques, while avoiding the drawbacks associated with selective epi growth.
It is an object of the present invention to provide a capacitor for a DRAM cell having a smaller cell area than prior cells, but without the adverse effects of selective epi growth.
It is a further object to provide a method for fabricating such a cell.
It is a further object of the invention to provide a method for fabricating a plurality of trench capacitors, using a single opening, for use in a reduced-area DRAM cell, the method using reactive ion etching and oxidation techniques to fabricate storage trenches at least partially under their respective cells' access device.
It is a further object of the invention to provide a trench capacitor for use in DRAM cells that has two storage trenches formed from a single trench opening.
The foregoing objectives are achieved by the present invention, which is a method, comprising: providing a substrate; forming a trench in the substrate, the trench having an opening of a first cross sectional area at the surface of the substrate; expanding that portion of the trench below a predetermined depth to a cross-sectional area larger than the first cross-sectional area; forming a dielectric layer on the wall of the trench in the expanded portion of the trench; filling the expanded portion of the trench with a polysilicon material; forming a partition in the polysilicon material to separate the polysilicon in a first portion of the expanded portion of the trench from the polysilicon in a second portion of the expanded portion of the trench.